module shuma(rst,clk,out,seg,b);
input rst;
input clk;
output seg,b;
output [7:0]out;
wire b;
wire [3:0] data;
divi a1(clk,rst,b);
counter a3(b,rst,data);
display a2(data,out,seg);
endmodule
module divi(clk,rst,newclk);
input clk;
input rst;
output newclk;
reg newclk;
reg [24:0] count;
always@(posedge clk)
begin
if(!rst)
begin
count<=0;
newclk<=0;
end
else
begin
count<=count+1;
if(count==25000000)
begin
newclk<=~newclk;
count<=0;
end
end
end
endmodule
module counter(clk,rst,out);
input rst;
input clk;
output [3:0]out;
reg [3:0] out;
always@(posedge clk)
begin if(!rst) out<=0;
else begin
out<=out+1;
if(out==10) out<=0;
end
end
endmodule
module display(in,out,seg);
input [3:0] in;
output [6:0] out;
output seg;
reg [7:0] out;
always@(in)
begin
case(in)
0:out=8'b0000_0011;
1:out=8'b1001_1111;
2:out=8'b0010_0101;
3:out=8'b0000_1101;
4:out=8'b1001_1001;
5:out=8'b0100_1001;
6:out=8'b0100_0001;
7:out=8'b0001_1011;
8:out=8'b0000_0001;
9:out=8'b0000_1001;
default:out=0;
endcase
end
assign seg=0;
endmodule
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